What you'll learn:
Learn the FPGA based AXI4 Bus Protocol, including AXI4-Lite and AXI4 Stream with RTL / Verification in VHDL and Verilog
AXI4 Bus signals and Master / Slave Handshaking
Verification of the AXI4 Protocol and interfacing to Vendor IP
Simulation Demonstrations in Verilog and VHDL with sample code files
Requirements:
Understand basic FPGA logic design in either VHDL or Verilog. Some experience with behavioral simulators can be helpful.
Description:
A full instructional series for all aspect of the AXI4 Bus protocol, including AXI4 Stream, AXI4-Lite, and AXI4. Each flavor of AXI4 has a bus flow, handshake, and signal requirements described in detail. An example implementation for a Master and Slave in each of the subsets of AXI4 are included, with simulation demonstrations using example testbenches in edaplayground, and vivado, included using the vivado block diagram with AXI4 Protocol checking.We learn the differences between each of the AXI4 flavors, where the AXI4 Stream protocol is used for uni-directional bulk data transfers from a master to a slave without addressing information. The AXI4 Stream protocol is the easiest to implement and the most common. The AXI4-Lite protocol is the other common interface that we learn how to implement. We get a full understanding of how the AXI4-Lite Master handshakes with the AXI4-Lite Slave with both address and data, and allows single word writes and reads, with slave responses on valid or error transactions. The full AXI4 protocol provides the highest data bandwith with burst modes up to 256 words of size 128 bytes. With 5 separate busses, including an Address Write Bus, a Data Write bus, an Address Read Bus, a Read Bus, and a Write Reponse bus, each with separate handshaking, there is an extensive understanding required to implement the RTL components successfully.
Who this course is for:
FPGA Logic designers and FPGA embedded software designers
